1. Field of the Invention
The invention relates to a data buffer memory of the "first-in, first-out" type, comprising logic for ensuring that, depending on the previously stored contents of the buffer, the input for data to be written is situated substantially as near as possible to the output for data to be read, thus providing substantially uninterrupted contents of the buffer. The invention includes an input bus by which data can be supplied to the buffer, that is, to an input of a register thereof assigned for this purpose, and an output which is connected to the last register of the buffer and on which data to be read appear.
2. Description of the Prior Art
A wide variety of data buffer memories of the first-in, first-out type are known to serve as buffer devices in digital data processing and communication systems at locations where differences occur in the rate in which input data is supplied and the rate in which output data is consumed. A number of the known buffers are distinguished by simplicity of construction, notably by a pronounced repetitive nature of the various sections of the buffer. An example is the buffer described in U.S. Pat. No. 3,745,535.
A problem encountered in buffers of this kind consists in that, if the capacity of the buffer amounts to n sections, a message which is supplied to an empty buffer appears on the output only after n clock pulse cycles. Particularly if n is large (&gt;32), unacceptable delays are then liable to occur in practice. These buffers are thus characterized as having a fixed input and a fixed output.
Also known are buffers which do not involve such a delay, because counting devices are used to ensure that a variable input location as well as a variable output location of the buffer can be activated, so that the data, especially in the "empty state" of the buffer, need not be transported through the entire register each time for transfer from an input to an output. Buffer devices of this kind are known from the British Patent Specification No. 1,479,774. A major problem occurring in buffer devices of this kind, however, is that the complexity of control strongly increases, notably in the case of buffers having a large number of sections. Counters having a high counting capacity and elaborate decoding and selection networks for the inputs and outputs to be assigned are required. Moreover, linking of a large number of small buffers in order to form a larger buffer is not possible without additional complications.
As the need for circuits and systems which are suitable for construction in solid-state integrated techniques increases, the interest in constructing buffer memories so that a repetitious character is obtained strongly increases. Moreover, the chances of linking a plurality of buffers without incurring additional complications are thus generally enhanced. A buffer of this kind which, moreover, does not involve the problem of long delay times as stated above, is known from U.S. Pat. No. 3,646,526. This Patent describes a buffer memory having a variable input and a fixed output, a marker bit indicating the location to which data must be supplied from an input bus to the buffer which thus has a variable input. This location is an empty cell which is situated nearest to the output of the buffer adjoining a series of filled cells between this input location and the output of the buffer. This buffer memory, however, has a special construction in which only one marker bit, being a control bit for the data section of the buffer, enables a data path of 1 bit. Therein, the situation arises in which given sections of this buffer device serve for transporting the marker bit as well as in the data bits. The risk of the occurrence of errors in this buffer, therefore, is real: if a 1 bit is incorrectly regarded as a marker bit, control of the data flow is disturbed. The risk of instability of the buffer, therefore, is not imaginary, because permanent uncertainty may arise with respect to the correct input location from the input bus to the buffer.